DC-DC converter for mobile application

ABSTRACT

A DC-DC voltage conversion provides a voltage to a processor in a mobile computer system using a high side power FET and a low side power FET, each having a variable gate discharge time dependent on the applied battery voltage. The power FETs are arranged in a synchronous totem pole configuration with a junction point therebetween, coupled between a voltage input terminal and ground, with the junction point coupled to a voltage output terminal. Each of the power FETs is driven by a FET driver, with the driver being coupled to the output of a comparator comparing a reference voltage with the output voltage. To avoid cross-conduction, the high side power FET and the low side power FET are coupled to each other in such a manner that the event of one turning off will turn on the other after a dead time determined by the threshold sense circuit, plus delays of the devices used in the embodiment.

BACKGROUND OF THE INVENTION

The present invention relates to DC-DC converters in general, and moreparticularly a DC-DC converter for use with mobile computers.

As described in the background portion of U.S. Pat. No. 5,534,771,assigned to Intel Corporation, the assignee of the present invention,integrated circuits utilized in computer systems typically requireseveral DC voltages, one of these being a voltage of about 5 volts tooperate TTL (Transistor-Transistor Logic) type devices and then lowervoltages to operate CMOS (Complimentary Metal Oxide Semiconductor)devices, and processors. Current processors such as PentiumPro®processors utilizing CMOS technology manufactured by the IntelCorporation for mobile use (e.g., laptop computers) operate on the orderof 2.9 volts. The processors in these computers, which are provided forthe mobile environment, typically require two processor voltages: a corevoltage and an I/O voltage. These voltages must be precisely regulated.

As is the case with the DC (direct current) to DC converter in U.S. Pat.No. 5,534,771, DC to DC converters typically are switching voltageregulators which are more efficient than linear regulators above a valueof about 200 mW load power. Although attempts have been made to reducethe cost of switching regulator converters, there is still a need tofurther reduce the cost by providing a design which can be implementedwith discrete components. In particular, there is a need for improvementin a type of switching circuit which arranges FETs (field effecttransistors) in a synchronous totem pole configuration to reduce lossesin the lower element by replacing the diode used in previous circuitswith a low on-resistance FET. In such a synchronous design, it isdesirable to prevent damaging crosscurrent conduction in the FETs and,in particular, for mobile applications, even nondamaging conduction isundesirable. The ability to do this with a minimum number of components,cost expense and minimal use of board real-estate, is also desirable andis important in the mobile application.

There is also a need for a low cost method of short circuit protectionto reliably turn off the output of the converter in the case of a shortcircuit. Furthermore, the design should take into consideration problemswhich can occur during start up, when the full voltage is not suppliedto the converter, and also problems associated, particularly in themobile environment, with turning the converter off or powering it downwhen it is not needed and the processor is in an inactive state. This isimportant to increase battery life.

SUMMARY OF THE INVENTION

These needs are solved by an embodiment of a DC-DC converter circuitwhich has a voltage input terminal and a voltage output terminal. Afirst comparator has a first input, coupled to a voltage reference and asecond input, coupled to the voltage output terminal. The comparator'soutput is eventually coupled to the inputs of a first FET driver and asecond FET driver. The FET drivers, respectively, drive a high sidepower FET and a low side power FET, each having a turn on time arrangedin a synchronous totem pole configuration, coupled between a voltageinput terminal and ground. The high side power FET and the low sidepower FET are coupled to each other in such a manner that the event ofone FET being sensed off will turn on the other FET after a status levelis sensed true.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an embodiment of a computer systemutilizing an embodiment of a DC-DC converter according to the presentinvention.

FIG. 2 is a circuit diagram of an embodiment of a DC-DC converteraccording to the present invention.

FIG. 3 is a circuit diagram of a FET driver constructed of discretecomponents useable in the embodiment of a DC-DC converter according toFIG. 2.

DETAILED DESCRIPTION

FIG. 1 is an overall diagram of a mobile computer system including anembodiment of the DC to DC converter(s) of the present invention.Although the voltage regulator described herein is an embodimentdirected specifically to a mobile computer requiring, e.g., outputvoltages of 5, 3.3 and 2.9V, the invention is not so limited.Embodiments for other computer systems and other electronic deviceswhich require DC-DC conversion can also be constructed in accordancewith the present invention.

The mobile computer system is powered by a DC power source 5 which willbe the mobile computer's battery or power source that is recharged froman AC (alternating current) to DC converter (not shown in FIG. 1). Amicrocontroller 10 within the computer system is powered by DC powersource 5 via a linear regulator 4. The linear regulator may have anoutput of 5V, for example. Its output is backdriven to 7V when a +5VDC-DC converter 3 is turned on as described below. DC power source 5also provides a voltage input Vdc (e.g., ranging between 5 and 18V) to+5V DC to DC converter 3, a DC-DC I/O (Input/Output) converter 6 (3.3V),and a DC-DC core converter 8 (2.9V), each constructed according to anembodiment of the present invention, such as that described below inconnection with FIG. 2. The output of +5V DC-DC converter 3 is providedas the voltage source for various TTL circuits 7. The outputs of DC toDC I/O converter 6, and DC-DC core converter 8 are supplied as the coreand I/O voltages of a processor 9, e.g., a PentiumPro® processor.

In conventional fashion, the microcontroller 10 monitors, e.g., a userinterface 26, and a battery charger 28 via lines 12 and 16 respectively.Microcontroller 10 also controls the turning on and off of the DC-DCconverters via ports 1 and 2. The output of port 1 is coupled to each ofthe converters 3, 6 and 8. When a port 1 output controlling V1 is atground, it effectively keeps high side FETs in converters 3, 6, and 8from draining the DC voltage source 5 when the converter is turned offas explained below. To activate the system, microcontroller 10 provides,at the port 1, a Vcc voltage V1, and then at a port 2, a sync outputwhich is coupled to +5V DC to DC converter 3 as its "sync" input.Converter 3 provides its voltage output as a sync input to I/O converter6, which in turn provides its voltage output as a sync input toconverter 8.

FIG. 2 is a circuit diagram of an implementation of an embodiment of thepresent invention which can be used as converters 3, 6 and 8 of FIG. 1.The circuit converts an input voltage Vdc, e.g., from voltage source 5of FIG. 1 at terminal 60 to an output voltage at terminal 21 bycontrolling the switching of two FETs 61 and 63 in a synchronous totempole configuration.

As illustrated in FIG. 2, a reference comparator 11 has its invertinginput coupled through a resistor 13 to the output of a voltage reference17. Reference 17 is coupled to a voltage input node 24 to which the"sync" voltage is supplied, for example, from microcontroller 10 oranother converter through a bias resistor 19. Resistor 19 is a pull-upresistor that provides bias current to the precision voltage reference17. Its value must also consider the current pulled by resistor 15 inaddition to the minimum current required for the reference itself (seeFIG. 1). Reference 17 may be a low-power type, e.g., having a biascurrent 60 uA, typical. This allows the bias resistor 19 to be madesufficiently large to reduce power consumption by the reference. Asexplained above, application of the voltage "sync" is used to turn theconverter on in a controlled manner. As also noted above, in theembodiment shown in FIG. 1, the 5V converter 3 obtains its sync inputfrom the microcontroller 10, the 3.3V I/O converter 6 obtains its syncinput from the output of 5V converter 3 and the 2.9V core converterobtains its sync voltage from the output of 3.3V converter 6. In thisway the processor 9 may receive both its voltages, e.g., both 3.3 and2.9V, in proper sequential timing as usually deemed necessary inprocessor applications.

The circuit uses voltage V1 as the operating voltage for comparator 11and other parts of the circuit. Voltage V1 is initially 5V±5%, although7V is preferred for the best circuit efficiency in driving FETs. In anoptional embodiment of the 5V converter 3 such an increase to 7V may beobtained from a special boost winding 34 of an inductor 33 in the outputcircuit of converter 3. A winding 34 and core is provided, in additionto inductor 33. The output of winding 34 is coupled through a diode 30(see FIG. 1) to the output of linear regulator 4. The cathode of diode30 is coupled to ground through a capacitor 32. The voltage across theprimary winding of inductor 33 is a constant 5V when inductor 33 isreleasing its stored energy, during operation of the converter to beexplained below. In other words, FET 61 is off and FET 63 is on. Byadding winding 34, the device becomes a transformer. In this embodiment,which is an option only in the 5V converter 3, the primary winding 33between terminals 70 and 21 may have 10 turns. The calculated boostfactor is 0.5V/turn. Placing five turns on the secondary will provide 7Vwhen the drop through diode 30 of FIG. 1 is included. Thus the +5Voutput is being boosted by 5 times 0.5V/turn or 2.5V. Diode 30 is backbiased when the alternate inductor phase occurs. Capacitor 32 suppliesenergy to the connected load until the boost winding recharges capacitor32. The boost winding eliminates the 1.2 w being dissipated in thelinear regulator at peak battery voltage conditions. This gives bettersystem efficiency.

The micro-controller 10 asserts its port outputs to be logic "one" orlogic "zero" as indicated in connection with FIG. 1. As noted above, aport 1 of microcontroller 10 provides V1 to each of comparators 3, 6 and8, then port 2 provides a sync input to the converter within the systemhaving the highest output voltage, in the example of FIG. 1, the 5Vconverter 3.

The inverting input of comparator 11 is also coupled through a resistor15 and capacitor 25 in parallel to ground. The circuit includingresistors 13 and 15 and capacitor 25 provide a network to condition theconverter's power-up response and divide down the reference voltage.Capacitor 25, in conjunction with resistor 13, causes the converter'soutput voltage to rise slowly on the output bulk capacitors 71 describedbelow and thus keeps peak currents minimized. Resistors 13 and 15 dividedown the reference voltage before the derivative is presented to theregulation comparator 11. Resistor 13 also isolates reference 17 fromdetecting capacitor 25 as a capacitive load, and eliminates possibleoscillation of the reference device.

The non-inverting input of comparator 11 receives the voltage Vout fedback from the output terminal 21 of the regulator circuit throughresistor 29. The non-inverting input is also coupled to the output ofcomparator 11 through a resistor 33 and is coupled to ground through acapacitor 31. The regulated output voltage, Vout, being provided by theconverter, in the illustrated embodiment, as noted above, is typicallyeither 5, 3.3 or 2.9V, but will vary, depending on the devices beingpowered. Comparator 11 compares the output voltage against a derivativeof the reference voltage being output by voltage reference 17 whichdefines what the output regulation value should be. In a mobile computerapplication, the regulated voltage supplied to the processor isgenerally set at the factory per mobile processor lot used. Resistors 29and 33 determine the amount of dc hysteresis to be applied to thecomparator's non-inverting input. Their design values provide finetuning of the switching frequency for this asynchronous style converter,and are chosen for optimal converter efficiency at nominal loading.Capacitor 31 in conjunction with resistor 29 provide high-frequencydecoupling if required.

The output voltage Vout at terminal 21 is also coupled through aresistor 37 to the non-inverting input of a short circuit protectioncomparator 35. The inverting input of comparator 35 is coupled to theinverting input of comparator 11, i.e., to the derivative of voltagereference 17. A capacitor 39 provides high-frequency decoupling of thenon-inverting input to ground. In addition, the voltage V1 at terminal22 is coupled through a resistor 41 to the non-inverting input ofcomparator 35. Comparator 35 has the function of protecting the powerFETs 61 and 63 (to be described below in more detail) from shortcircuits. A short circuit is defined as a negative-going abnormaltransient that exceeds the factory-fixed offset provided by the tworesistors 37 and 41 on the non-inverting input of comparator 35. Theamount of offset is obtained by multiplying (V1-Vout) by the ratio ofthe voltage divider comprising resistor 37 and resistor 41, i.e., theresistance of resistor 37/(the resistance of resistor 37+the resistanceof resistor 41).

At least the "sync" voltage at node 24 providing power to the reference17 via resistor 19, must be re-cycled to clear the latch-off of thecircuit. Recycling of this voltage and the voltage V1 at terminal 22 isalso possible. In an embodiment such a FIG. 1, with more than oneconverter, regardless of which converter output was shorted, themicrocontroller 10 will have to remove power from the first voltagereference in the series of converters (see FIG. 1), to eventually clearthe fault. During the fault no converter will be in an overcurrentcondition because the anti-ring diodes inside the processor chip setwill remain back-biased, as is true even during normal operation.

Thus, resistors 37 and 41 form a two-resistor network which provides anoffset voltage applied to the non-inverting input of comparator 35 tobe, e.g., 250 millivolts above the reference voltage at node 40, i.e.,at its inverting input. The amount of offset required, takes intoconsideration the expected transient deviation of the connected load,e.g., a processor, plus some guard band to prevent false tripping. Whenthe short-circuit condition occurs, i.e., Vout has fallen, e.g., 250millivolts below the reference, the output of comparator 35 negates theundesirable forthcoming action of comparator 11 by pulling down on theinput of a FET driver 47. The converter goes into a latched-offcondition causing FET 61 to shut off and voltage Vout to go to zero.After the condition for short-circuit has been removed, the operation ofthe converter is restored by re-cycling the voltage specifically atterminal 24, i.e., the top side of resistor 19. As noted above, it ispermissible to recycle this and all V1 nodes at once without endangeringthe power FETs 61 and 63. To bring the converter outputs down in afaster and more orderly fashion, the "sync" input to +5V converter 3provided by the microcontroller port 2 is first brought low. Then afteranother port 3 senses Vcore decreasing below zero via line 14, themicrocontroller sets the V1 port 1 to zero volts. (see FIG. 1).

FET driver 47 has three sources of input with an output having a NANDresult. Any source can inhibit high-side power FET 61 by pulling low onthe input of the FET driver 47. The output of comparator 11 is coupledthrough pull-up resistor 43 to voltage V1. This output point is coupledto the gate of an n-channel signal FET 45 the output of which is coupledto the input of a FET driver 47. FET 45 is coupled to V1 through apull-up resistor 57 at its output to provide a pull-up for the FETdriver input. N-channel signal FET 45 inverts the signal from comparator11 and comparator 35 or signal FET 65 to also inhibit the high-sidepower FET 61. At the input of inverting FET driver 47 (i.e., at node77), a low level from any of FET 45, FET 65 or comparator 35 will turnoff FET 61.

The output of comparator 11 is also coupled to the gate of a p-channelsignal FET 51 the output of which is coupled through a Shottky diode 52to a FET driver 53. N-channel FET 51 disallows power FET 63 from being"on" at the same time as FET 61, and prevents cross-conduction currentthat might flow from Vdc to power ground through both FETs 61 and 63. Inthe illustrated embodiment, a suggested value for Rds₋₋ on in FET 51 isless than 10 ohms, preferably one ohm if the tapped inductor option,i.e., winding 34 is not utilized in +5V converter 3. The source of FET51 is coupled directly to V1. A decoupling capacitor 59 provides a localcurrent source for a momentary peak current, drawn through the p-channelFET 51 caused by a terminating resistance 69 described in more detailbelow. In one embodiment a resistance of about 100 ohms has been foundto be a good value for the reasons set out below.

Shottky diode 52 prevents the backflow of current from voltage node 70to V1 via the path of the driving resistance 69. A value of about 100ohms for resistor 69 provides optimal dead time efficiency by quicklydriving the input of FET driver 53 low when node 70 drops below thethreshold of the input of FET driver 53. Although it is possible todesign-out diode 52 by increasing driving resistance 69, this willdegrade the converter's efficiency by delaying the turn-on of FET 63.

Diode 52 and resistor 69 form a NOR function to turn off and keep offFET 63 respectively. The input at FET driver 53 will be high if FET 51is on or if the voltage at node 70 is high. Similarly, the output of FETdriver 53 is coupled to low-side N-channel power FET 63. The circuitdesign of this embodiment requires the input threshold for FET driver 47to be in the range of 0.4V to 4.3V and that of FET driver 53 to be inthe range of 0.4V to 3.6V. High side power FET 61 in this embodiment isa p-channel type having a low Rds₋₋ on. In particular, a 4435 iscurrently the optimal device. Low-side power FET 63 provideshigh-converter efficiency. In particular, a 4410 has been found to workwell. Of course, the invention is not limited to these devices. In theillustrated embodiment, the usual Shottky diode bypass agent on FET 63is omitted. This embodiment of the converter allows usage of the FET'sinternal diode during the dead time interval. No significant power lossoccurs if the time is kept brief.

The power path input voltage Vdc at terminal 60, to be converted, whichalso provides the operating voltage for FET drivers 47 and 53, iscoupled to the source of FET 61. Typically, in an embodiment for usewith a mobile computer, Vdc is in the range of 5V to 18V. This node 60should have surge protection (not shown) to protect the gates of thepower FETs 61 and 63 from exceeding Vgs₋₋ max. A decoupling capacitor 67couples Vdc to ground. It is located by the Vcc input pin of FET driver47 and 53 to eliminate any high-frequency noise from entering theinternal digital portion of FET drivers 47 and 53. Noise is caused bythe switching of high-currents through the circuit board. Capacitor 62provides bulk stored energy for FETs 61 and 63.

The drain of FET 61 is coupled to the drain of FET 63, the source ofwhich is coupled to ground. The junction 70 between the drain of FET 61and drain of FET 63 is coupled to inductor 33, the output of whichprovides the output voltage of the DC-DC converter, Vout, at outputterminal 21. In one embodiment, inductor 33 may be an averaging inductorthat should be made from low-loss core material and optimal wire sizingto result in optimal converter efficiency for the mobile environment.Vout terminal 21 is coupled to ground through one or more capacitorsproviding a bulk capacitance 71. This provides bulk decoupling thatmeets the step-current and capacity requirements of the connected load,for instance a processor with which the converter is used, e.g. an IntelPentium® processor. When the system, e.g., a computer system with whichthis embodiment of the converter is used, is turned off, the charge ofthe output capacitors 71 may be bled away through the use of theinductor 33 and low-side FET 63. This method uses the parts already inthe circuit, which avoids additional expense of adding specialized partsfor this bleeding function. This bleeding occurs as soon as the voltageat terminal 21 discharges below the input threshold at FET driver 53 aswhen a short condition latches off the converter. Bleeding will alsooccur when a sync is set to zero by the microcontroller port 2 or theprevious converter output.

The input of FET driver 47 is coupled through an n-channel signal FET 65to ground to disallow power FET 61 from being "on" at the same time asFET 63. This prevents a cross-conduction current that might flow fromVdc to power ground through both FETs. FET 65 has its gate coupled tothe output of FET driver 53, and senses the moment when the stored gatecharge has been completely drained off the power FETs 11 gate.

Resistor 69 couples the output from FETs 61 and 63 to the input of FETdriver 53. This small-wattage resistor operates in high-peak powercondition, but low average power. As noted above, in one embodiment, 100ohms has been found to be a good value for this resistor. In operation,when the regulation comparator 11 wants to turn-off the low side FET 63,its output goes low, causing p-channel FET 51 to impress voltage V1minus one diode drop, across the resistor 69. The opposite end ofresistor 69 is at approximately ground potential, due to power FET 63still being in its turned-on state. When the impressed voltage exceedsthe input threshold level of the FET driver 53, its output changes stateand thereby turns off the low-side power FET 63. The length of the peakpower pulse applied across resistor 69, is the short dead-time intervaldetermined by the additive effects of the input to output delay time ofFET driver 53, FET 65 parasitic capacitances, and the widely variablepower-path source voltage Vdc at terminal 60, until the time thepolarity of inductor 33 reverses. For the illustrated embodiment, theaverage power dissipation of the, e.g., 100 ohm termination resistor 69,as a result of the pulsed activity is less than 3 milliwatts. Thevariation in the power-path source voltage, e.g., the battery voltageresults in a variation in the gate discharge time of the power FETs.Operation of the illustrated embodiment of the circuit of the presentinvention is not affected by these variations in gate discharge times.

Once the low-side FET 63 has been turned off, it can be seen that then-channel signal FET 65 has also been turned off. This now results inthe input to the high-side FET driver 47 being pulled up to V1 bypull-up resistor 57. When its input threshold level is exceeded, theoutput of FET driver 47 changes to a low-state, resulting in the turn-onof the high-side p-channel power FET 61. Also, a desirable positivefeedback situation occurs when the resistor 69 drives the input of theFET driver 53 toward a level of Vdc at terminal 60 via power FET 61,therefore ensuring complete turn-off of the low-side FET 11, even inpoor circuit board layout conditions.

When the comparator 11 senses the need to turn off the high-side powerFET 61 to maintain precise regulation, the comparator output goes high,being pulled up through resistor 43. Through the path of FET 45 and FETdriver 47 the power FET 61 is turned off. When high-side power FET 61 isturned off, the averaging inductor 33 causes current to flow from thepower ground, proceeding through the internal diode of the low-sidepower FET 63, and then towards the inductor. Any prolonged usage of theinternal diode of FET 63 to conduct this current would result indegradation in efficiency performance. However this is not the case inthe illustrated embodiment, since resistor 69 is pulling the input ofFET driver 53 to slightly below ground, and the gate of FET 63 is drivenhigh, making FET 63 conduct current more efficiently.

As can be seen from the description above, FETS 61 and 63, arranged in atotem pole configuration, operate in a synchronous manner, such thatwhen FET 61 is turned on, FET 63 is turned off and vice versa. Toprevent both FETs from being on at the same time, i.e. to prevent crossconduction due to gate drive overlap, two nodes are sensed for statusvoltage level. This is accomplished using low-cost, discrete components.N-channel signal FET 65 has an intrinsic threshold reference for sensingthe status voltage node located at the junction 75 of the low-side powerFET 63 and its driver 53. In this embodiment, the high-side driver 47input is not allowed to go high until the low-side power FET's gate hasbeen driven below the Vgs threshold of FET 65. Therefore, FET 65 isrequired to have a gate threshold voltage that is less than or equal tothe gate threshold voltage of the low-side power FET 63. Otherwise, ifthe sensing FET 65 has a threshold above that of the low-side FET, therecomes a dependance upon the propagation delays of the devices (which isundesirable) unless this delay is consistent and results in better costsavings.

The resistor 69 senses the other status voltage node 70 located at thejunction of the two totem-pole power FETs 61 and 63. The status node 70waits for a response of the inductor 33 before allowing the low-sideelement to conduct more efficiently. Until the low-side FET gate isdriven high, the peak power dissipated in the intrinsic diode is high.In this embodiment, it is precisely sensed when the inductor hasreversed its polarity in response to high-side power FET 61 turning off.The release of energy from the inductor 33 causes a current to flow fromthe power ground, proceeding through the intrinsic diode containedwithin the low-side power FET 63, and then continues the flow towardsthe inductor 33. When the diode conducts, node 70 has fallen to 0.7Vbelow ground. This status level signals the low-side FET driver 53 todrive high the low-side power FET 61 into better conduction efficiency.

This break-before-make method automatically compensates for widevariance in the input supply voltages. It also compensates for variancein the delay times of FET drivers, making matched drivers anon-necessity, compensates for the variance in the source and sinkimpedance of the drivers and the parasitics of the FETs.

This design utilizes a low-cost, innovative method of short-circuitprotection. Comparator 35 provides output short circuit protection bydetecting a condition when the output voltage is lower than thereference voltage. The output of comparator 35 will turn off FET 61through FET driver 47 and go into a latch condition. As noted above, ashorting condition exists when the reference voltage is more than, e.g.,250 millivolts (a design variable) above the instantaneous outputvoltage. Comparator 35 actively senses for the presence of a shortcircuit condition under turn-on, steady-state, and dynamic operation ofthe converter. The circuit is self-latching.

At least some comparators, such as the LM393 comparator, which can beused in the illustrated embodiment, have one bad effect when a Vccoperating voltage is applied to them. Until the Vcc, in this case V1,voltage is above 2V, the output gives an unexpected high state. In otherwords, the output response does not track the input signal levelsapplied to its inputs, in this case Vout and the reference voltage. Whenthe Vcc has risen above 2V, the output gives the expected switchingstates at the converter power-up transient. Because of this problem withcomparators, the state levels of the included control devices, spanningfrom comparator 11 to power FET 61, during the power-up interval, aresuch as to keep power FET 61 turned off. This is also true during steadystate operation, whereas, when comparator 11 output is asserted high,the power FET 61 will be turned off. Thus, the erroneous output state ofthe typical comparator with its Vcc supply still below 2V, is cured inthis design, and protects the output capacitors from damaging inrushcurrents at power-up of the circuit's V1 supply.

The power path input voltage Vdc does not require special interruptionwhen the converter is turned off. The V1 voltage asserted to the lowstate by microcontroller 10, pulls down the input of FET driver 47 viaresistor 57 and effectively keeps the high-side FET from draining thebattery. The FET drivers 47 and 53 are always powered by Vdc.Fortunately, the design allows the input of both of FET drivers 47 and53 to be set to zero volts when the converter is turned off. The FETdrivers 47 and 53 pull only 0.6 milliamps under these conditions.Otherwise 10 times more current would be drawn from the battery. Forsynchronous style converters running at zero load, there is about 15 mWpower path losses plus -250 mW of fixed losses due to switching. Theselosses will cease when the converter is powered down.

The integrated FET drivers 47 and 53 can be replaced by a discreteversion shown in FIG. 3 which is comparatively less expensive. Anotheradvantage of using the discrete version is the opportunity it providesto run each driver from more appropriate Vcc voltage sources. Sourcingthe low-side gate drive 53 from +5V or +7V (7V preferred), rather thanVdc will result in better converter efficiency. Some integrated FETdrivers have an input diode clamp to the driver's Vcc pin. These are notcompatible with the embodiment of the present invention described abovewhere Vcc is 5-7V yet the input of the FET driver is being drivenupwards of 18V via the resistor 69. This clamp diode will cause unwantedpower dissipation to occur and also cause poor regulation of V1. Theembodiment shown in FIG. 3, however, has no input diode clamp presentand is therefore a better method for driving the low-side power FET 63.The high-side FET driver 47 requires the same voltage source Vdc as thep-channel power FET it drives.

In the embodiment of FIG. 3, the input of the driver is coupled to thegate of a FET 81. The source of FET 81 is coupled to ground and itsdrain coupled through a resistor 82 to Vcc. The junction between thedrain of FET 81 and resistor 82 is also coupled to the base of atransistor 83 and the cathode of diode 84. The emitter of transistor 83is coupled to the output 86 of the circuit and to the anode of a diode84. In operation, transistor 83 is used to drive the output of thedriver circuit high. Diode 84 and FET 81 are used to drive gate 83 low.In other words, with a low input, FET 81 is turned off and the voltageon the base of transistor 83 turns it on to provide a high voltage atoutput 86. When the input goes high, FET 81 is turned on, turning offtransistor 83 and at the same time coupling the output 84 to ground.

The circuits of FIG. 2 and FIG. 3 can be manufactured with conventionalcomponents available from a number of different sources. Of course,implementation of these embodiments is not limited to the use of thosecomponents. Other components which can provide the necessary switchingcan be equally well used. These and other modifications can be madewithout departing from the spirit of the invention which is intended tobe limited solely by the appended claims.

What is claimed is:
 1. A DC-DC converter circuit comprising:a. a voltageinput terminal; b. a voltage output terminal; c. a voltage reference; d.a first comparator having a first input coupled to said voltagereference and a second input coupled to said voltage output terminal andan output; e. a first FET driver having an input coupled to the outputof said first comparator and an output; f. a second FET driver having aninput coupled to the output of said first comparator and an output; g. ahigh side power FET and a low side power FET arranged in a synchronoustotem pole configuration with a junction point between said high sidepower FET and said low side power FET, coupled between said voltageinput terminal and ground, said junction point coupled to said voltageoutput terminal; h. said high side power FET having a control inputcoupled to the output of said first FET driver; i. said low side powerFET having a control input coupled to the output of said second FETdriver; and j. said high side power FET and said low side power FETcoupled to each other in such a manner that an event of one turning offwill turn the other on after a status level is sensed true.
 2. A DC-DCconverter circuit according to claim 1 wherein said coupling of saidhigh side power FET and said low side power FET to each other includes afirst threshold sensing circuit coupled between the output of saidsecond FET driver and the input of said first FET driver.
 3. A DC-DCconverter circuit according to claim 2 wherein said first thresholdsensing circuit comprises a first signal FET.
 4. A DC-DC convertercircuit according to claim 3 wherein said coupling of said high sidepower FET and said low side power FET to each other further includes asecond threshold sensing circuit coupled between the output of said highside and low side power FET and the input of said second FET driver. 5.A DC-DC converter circuit according to claim 4 wherein said secondthreshold sensing circuit comprises a second signal FET.
 6. A DC-DCconverter circuit according to claim 5 and further including a Shottkydiode coupled between said second signal FET and said second FET driver.7. A DC-DC converter circuit according to claim 6 and further includinga resistor coupling the junction of said high side power FET and saidlow side power FET to the input of said second FET driver.
 8. A DC-DCconverter circuit according to claim 7 and further including a secondcomparator having a first input coupled to said voltage referencederivative, and a second input coupled to a source of voltage having avalue offset from said output voltage and an output coupled to saidfirst FET driver.
 9. A DC-DC converter circuit according to claim 8 andfurther including a second input voltage terminal and wherein the sourceof voltage, having a value offset from the output voltage comprises aresistor divider having a junction point coupled to said second input ofsaid second comparator, said resistor divider coupled across said outputvoltage terminal and said second input voltage terminal.
 10. A DC-DCconverter circuit according to claim 9 and further including a thirdsignal FET having a gate coupled to the output of said first comparatorand having an output terminal, a pull-up resistor coupling said outputterminal to said second voltage input terminal and said output terminalcoupled to said input of said first FET driver.
 11. A DC-DC convertercircuit according to claim 9 wherein signals from the output of saidsecond comparator and said first signal FET are ORed at said outputterminal of said third signal transistor.
 12. A mobile computer systemcomprising:a. a processor; b. a first DC-DC converter circuitcomprising:i. a voltage input terminal; ii. a voltage output terminal;iii. a voltage reference; iv. a first comparator having a first inputcoupled to said voltage reference and a second input coupled to saidvoltage output terminal and an output; v. a first FET driver having aninput coupled to the output of said comparator and an output; vi. asecond FET driver having an input coupled to the output of saidcomparator and an output; vii. a high side power FET and a low sidepower FET arranged in a synchronous totem pole configuration with ajunction point between said high side power FET and said low side powerFET, coupled between said voltage input terminal and ground, saidjunction point coupled to said output terminal; viii. said high sidepower FET having a control input coupled to the output of said first FETdriver; ix. said low side power FET having a control input coupled tothe output of said second FET driver; and x. said high side power FETand said low side power FET coupled to each other in such a manner thatan event of one turning off will turn on the other after a status levelis sensed true.
 13. A mobile computer system according to claim 12wherein said coupling of said high side power FET and said low sidepower FET to each other includes a first threshold sensing circuitcoupled between the output of said second FET driver and the input ofsaid first FET driver.
 14. A mobile computer system according to claim13 wherein said first threshold sensing circuit comprises a first signalFET.
 15. A mobile computer system according to claim 14 wherein saidcoupling of said high side power FET and said low side power FET to eachother further includes a second threshold sensing circuit coupledbetween the output of said high side and low side power FET and theinput of said second FET driver.
 16. A mobile computer system accordingto claim 15 wherein said second threshold sensing circuit comprises asecond signal FET.
 17. A mobile computer system according to claim 16and further including a Shottky diode coupled between said second signalFET and said second FET driver.
 18. A mobile computer system accordingto claim 17 and further including a resistor coupling the junction ofsaid high side power FET and said low side power FET to the input ofsaid second FET driver.
 19. A mobile computer system according to claim18 and further including a second comparator having a first inputcoupled to said voltage reference and a second input coupled to a sourceof voltage having a value offset from said output voltage an outputcoupled to said first FET driver.
 20. A mobile computer system accordingto claim 19 and further including a second input voltage terminal andwherein source of voltage having a value offset from the output voltagecomprises a resistor divider having a junction point coupled to saidsecond input of said second comparator, said resistor divider coupledacross said output voltage terminal and said second input voltageterminal.
 21. A mobile computer system according to claim 20 and furtherincluding a third signal FET having a gate coupled to the output of saidfirst comparator and having an output terminal, a pull-up resistorcoupling said output terminal to said second voltage input terminal andsaid output terminal coupled to said input of said first FET driver. 22.A mobile computer system according to claim 21 wherein signals from theoutput of said second comparator and said first signal FET are ORed atsaid output terminal of said third signal transistor.
 23. A mobilecomputer system according to claim 22 and further including:a. a dcpower source having a first voltage output coupled to said voltage inputterminal; b. a first voltage source providing a second voltage outputcoupled to said second input terminal; and c. a second voltage sourceproviding a third voltage output coupled to said voltage reference. 24.A mobile computer system according to claim 23 and further including:a.a linear voltage converter having said first voltage output as an inputand as providing as an output said second voltages; b. a microcontrollerhaving said second voltage as an input and having first and secondoutput ports at which said second voltage is selectively present; c.second and third DC-DC converter circuits identical to said firstvoltage invention; outputting respectively first second and thirdconverted voltages at their respective output terminals; d. said firstport coupled to the second input terminal of each of said first, secondand third DC-DC converters; e. said second port coupled to said voltagereference of said first DC-DC converter; f. said first converted voltagecoupled to said voltage reference of said second DC-DC converter; g.said second converted voltage coupled to said voltage reference of saidthird DC-DC converter; h. TTL circuits having a voltage input coupled tosaid first converted input; and i. said second and third convertedvoltages coupled to said processor.
 25. A method of carrying out a DC-DCvoltage conversion using a high side power FET and a low side power FET,each having a gate with a variable discharge time dependent on appliedvoltage, arranged in a synchronous totem pole configuration with ajunction point between said high side power FET and said low side powerFET, coupled between an voltage input terminal and ground, the junctionpoint coupled to a voltage output terminal, each of the power FETs beingdriven by a FET driver, said driver being coupled to the output of acomparator comparing a reference voltage with the output voltage, themethod comprising:a. coupling said high side power FET and said low sidepower FET to each other in such a manner that an event of one turningoff will turn on the other after a status level is sensed true.
 26. Themethod according to claim 25 and further including sensing a shortcircuit condition with a second comparator and turning off said highside FET in response to detecting a short circuit.
 27. The methodaccording to claim 26 and further including latching said comparatorwhen a short circuit is detected.
 28. The method according to claim 25wherein said DC-DC conversion is carried out in a mobile computer havinga battery and said applied voltage is the voltage of said battery.